國防科學技術大學計算機學院 410073
摘要：提出了一種基于時序等價性檢查技術的組合邏輯單元系統級可靠性分析理論和方法，并基于VIS 系統下用 C 語言實現了原型工具。實驗結果表明本方法可以成功篩選出邏輯電路中的敏感點，為后續優化設計提供指導。
關鍵字：軟錯誤；可靠性分析；邏輯電路
Soft Error Reliability Evaluation of Combinational Logic Element
Sun Jin-Yin Li Tun
Department of Computer Science and Technology, National University of Defense Technology, Chang sha 410073
Abstract: A sequential equivalence checking based approach for system level soft error reliability evaluations proposed. It’s prototype tool is accomplished in C language on the VIS system. Experimental results show that our approach can select soft error vulnerable spots, it is useful for the optimal design.
參考文獻
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作者簡介：孫金銀（1984—），男，碩士，主要研究領域為電路容錯與可靠性。李暾(1974－),男,博士,副教授,主要研究領域為形式化技術,并行模擬,微處理器驗證,電子 CAD 等。
